Method of manufacturing semiconductor device

ABSTRACT

A false report on appearance inspection of a semiconductor device is prevented by suppressing variation in surface state of an electrodeposited gold electrode. In formation of an electrodeposited gold electrode, an electrodeposited gold electrode comprised of a plurality of electrodeposited gold layers in the stack is formed by alternately repeating a step of performing energization between an anode electrode and a cathode electrode provided in a treatment cup of a plating apparatus to cause crystal growth of an electrodeposited gold layer (energization ON), and a step of performing no energization between the anode electrode and the cathode electrode (energization OFF). Consequently, even if aging variation occurs in composition of the plating solution, variation in surface state of the electrodeposited gold electrode is suppressed, and a surface state with a surface roughness of, for example, about 0.025 rad can be maintained.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2014-009004 filed onJan. 21, 2014 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a technique for manufacturing asemiconductor device, the technique being preferably used for, forexample, a manufacturing process of a semiconductor device having anelectrodeposited electrode formed by an electrolytic plating process.

Japanese Unexamined Patent Application Publication No. 2011-105968describes a technique in which a voltage applied to a plating solutionis monitored during a step of forming a gold bump electrode by anelectrolytic gold plating technique using a non-cyanide platingsolution, thereby the amount of thallium added to the plating solutionis detected to suppress occurrence of inferior plating such as anomalousdeposition due to decrease in concentration of added thallium.

SUMMARY

There have been a large number of reports on anomalous appearance, whichis found in appearance inspection of a semiconductor device, of anelectrode formed on a main surface of a semiconductor substrate by anelectrolyte gold plating process (hereinafter referred to aselectrodeposited gold electrode). However, most of such reports onanomalous appearance have been false reports in which gold precipitatesare detected as foreign substances while they are essentially notnecessary to be detected as foreign substances. Such false detection iscaused by gradual change of a surface of the electrodeposited goldelectrode from a rough state to a smooth state due to aging variation incomposition of the plating solution. It has been therefore necessary tosuppress variation in surface state of the electrodeposited goldelectrode in order to decrease the false reports on appearanceinspection of a semiconductor device.

Other issues and novel features will be clarified from the descriptionof this specification and the accompanying drawings.

According to an embodiment of the present invention, there is provided amethod of manufacturing a semiconductor device, in which when anelectrodeposited gold electrode is formed by an electrolytic goldplating process, a step of performing energization between an anodeelectrode and a cathode electrode provided in a treatment cup of aplating apparatus to cause crystal growth of a electrodeposited goldlayer, and a step of performing no energization between the anodeelectrode and the cathode electrode are alternately repeated, thereby anelectrodeposited gold electrode comprised of a plurality ofelectrodeposited gold layers in the stack is formed.

According to the embodiment of the invention, since variation in surfacestate of the electrodeposited gold electrode can be suppressed, a falsereport on appearance inspection of a semiconductor device can beprevented.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a major-part section diagram of a semiconductor device duringa manufacturing process of an electrodeposited gold electrode accordingto an embodiment of the invention.

FIG. 2 is a major-part section diagram of the same portion as that ofFIG. 1 during the manufacturing process following FIG. 1.

FIG. 3 is a major-part section diagram of the same portion as that ofFIG. 1 during the manufacturing process following FIG. 2.

FIG. 4 is a major-part section diagram of the same portion as that ofFIG. 1 during the manufacturing process following FIG. 3.

FIG. 5 is a major-part section diagram of the same portion as that ofFIG. 1 during the manufacturing process following FIG. 4.

FIG. 6 is a major-part section diagram of the same portion as that ofFIG. 1 during the manufacturing process following FIG. 5.

FIGS. 7A and 7B are each a major-part section diagram of a treatment cupprovided in a first plating apparatus according to this embodiment, thetreatment cup being structured to stir a plating solution with astirrer.

FIG. 7A is a major-part section diagram illustrating an aspect of thetreatment cup of the first plating apparatus when a semiconductor waferis set therein or removed therefrom, and FIG. 7B is a major-part sectiondiagram illustrating an aspect of the treatment cup of the first platingapparatus when a semiconductor wafer is subjected to plating.

FIG. 8 is a process flowchart of a plating process using the firstplating apparatus according to this embodiment.

FIG. 9A is a schematic illustration of a recipe configuration in platingusing the first plating apparatus according to this embodiment, and FIG.9B is a schematic illustration of a recipe configuration in platingusing the first plating apparatus in a comparative investigation by theinventors.

FIG. 10A is a section diagram schematically showing an electrodepositedgold electrode according to this embodiment, and FIG. 10B is a sectiondiagram schematically showing an electrodeposited gold electrode in acomparative investigation by the inventors.

FIG. 11 includes a graph showing surface roughness of anelectrodeposited gold electrode according to this embodiment with eachof energization ON time and energization OFF time as a parameter, and atable collectively showing the energization ON time and the energizationOFF time for each semiconductor wafer.

FIG. 12 is a major-part section diagram of a treatment cup provided in asecond plating apparatus according to this embodiment, the treatment cupbeing structured to stir a plating solution with a jet.

FIG. 13A is a schematic illustration of a recipe configuration inplating using the second plating apparatus according to this embodiment,and FIG. 13B is a schematic illustration of a recipe configuration inplating using the second plating apparatus in a comparativeinvestigation by the inventors.

DETAILED DESCRIPTION

Although the following embodiment may be dividedly described in aplurality of sections or embodiments for convenience as necessary, theyare not unrelated to one another except for the particularly definedcase, and are in a relationship where one is a modification, a detail,supplementary explanation, or the like of part or all of another one.

In the following embodiment, when the number of elements and the like(including the number, a numerical value, amount, a range, etc.) arementioned, the number is not limited to a specified number except forthe particularly defined case, or the case where the number isprincipally clearly limited to the specified number. In other words, thenumber may be not less than or not more than the specified number.

In the following embodiment, it will be appreciated that aconstitutional element (including an element step etc.) of theembodiment are not necessarily indispensable except for the particularlydefined case and for the case where the constitutional element isconsidered to be principally clearly indispensable.

It will be appreciated that the term “comprised of A”, “configured ofA”, “having A”, or “including A” is not intended to exclude any elementother than the element A except for the case where the element A isparticularly defined to be exclusive, for example. Similarly, in thefollowing embodiment, description on a shape of a constitutional elementetc., a positional relationship, or the like is intended to include anelement etc. having a shape or the like substantially similar to that ofthe constitutional element etc. except for the particularly defined caseand for the case where such an element etc. is considered to beprincipally clearly not included. The same holds true in each of thenumerical value and the range.

In drawings used in the following embodiment, a plan diagram may also behatched for better viewability. In all drawings for explaining thefollowing embodiment, components having the same function are inprinciple designated by the same numeral, and duplicated description isomitted. Hereinafter, an embodiment of the invention is described indetail according to the accompanying drawings.

The inventors have found issues in appearance inspection of asemiconductor device, and the issues are now specifically describedsince the method of manufacturing a semiconductor device according tothe embodiment of the invention is considered to be further clarifiedthereby.

The inventors adopts an electrodeposited gold electrode that is formedon a pad electrode with a seed film therebetween by an electrolytic goldplating process, i.e., adopts an electrode having a so-called over padmetallization (OPM) structure, as an external electrode provided in thesemiconductor device for electrical coupling to an external component.However, there has been reported anomalous appearance of theelectrodeposited gold electrode, which is found in appearance inspectionof a semiconductor device, while the reported anomalous appearance isessentially not anomalous appearance. The inventors therefore have madeinvestigations on a cause of such false inspection and a measure againstthat.

In a step of forming the electrodeposited gold electrode, as the numberof times of treatment or the lapse of time from initial make-up ofelectrolytic bath increases, aging variation occurs in composition of aplating solution, and thus a surface of the electrodeposited goldelectrode is gradually changed from a rough state to a smooth state. Inaddition, visual brightness of the electrodeposited gold electrodevaries depending on a surface state of the electrodeposited goldelectrode. Specifically, an electrodeposited gold electrode having arough surface (for example, surface roughness of 0.025 rad or more)shows dark appearance in appearance inspection, while anelectrodeposited gold electrode having a smooth surface (for example,surface roughness of less than 0.025 rad) shows bright appearance in theappearance inspection.

Hence, in the step of forming the electrodeposited gold electrode, asthe number of times of treatment or the lapse of time from initialmake-up of electrolytic bath increases, appearance of theelectrodeposited gold electrode is gradually changed from a dark stateto a bright state.

In the step of forming the electrodeposited gold electrode, a goldprojection having a size of 20 to 100 μm in diameter may be formed dueto precipitation of gold. Even if such a gold projection is formed onthe surface of the electrodeposited gold electrode, a trouble such assignificant reduction in yield of a semiconductor device does not occur;hence, the gold projection may be formed. In appearance inspection, evenif the gold projection exists on the electrodeposited gold electrodehaving a dark appearance (the electrodeposited gold electrode having arough surface), the gold projection is not recognized and theelectrodeposited gold electrode is determined to be normal inappearance.

However, if the gold projection exists on the electrodeposited goldelectrode having a bright appearance (the electrodeposited goldelectrode having a smooth surface), the gold projection is recognized asa foreign substance in appearance inspection, and thus theelectrodeposited gold electrode is determined to be anomalous inappearance while being essentially normal.

Consequently, it has been understood that the surface of theelectrodeposited gold electrode is necessary to be kept rough, forexample, 0.025 rad or more, so that the gold projection is notrecognized in appearance inspection, in order to decrease the falsereports on appearance inspection of a semiconductor device. The surfaceof the electrodeposited gold electrode can be kept rough by controllinga concentration ratio of sulfurous acid to sulfuric acid contained in aplating solution. However, such a method requires replacement of theplating solution or addition of sulfurous acid, leading to increase inmanufacturing cost.

First Embodiment

<Manufacturing Process of Electrodeposited Gold Electrode>

A method of manufacturing a semiconductor device according to a firstembodiment is described in step order with FIGS. 1 to 6. FIGS. 1 to 6are each a major-part section diagram of a semiconductor device forexplaining a manufacturing process of the electrodeposited goldelectrode.

First, as illustrated in FIG. 1, a semiconductor substrate, which is asemiconductor wafer SW processed into a thin circular sheet shape inthis exemplary case, is prepared, and a plurality of semiconductorelements, multilayer-structured interconnections, and the like, whichare each omitted to be shown, are formed on a main surface of thesemiconductor wafer SW. Furthermore, a surface protection film IL1covering the multilayer-structured interconnections and the like isformed, and then pad electrodes PD including, for example, aluminum as amain conductor are formed, each pad electrode PD being to beelectrically coupled to, for example, a top interconnection of themultilayer-structured interconnections. The pad electrode PD is formedby forming an aluminum film on the main surface of the semiconductorwafer SW by, for example, a sputtering process, and then processing thealuminum film by a photolithography process and a dry etching process.The pad electrode PD has a thickness of about 1 μm, for example.Although the pad electrode PD includes aluminum as the main conductor inthe first embodiment, the pad electrode PD may include copper as themain conductor.

Subsequently, as illustrated in FIG. 2, a silicon oxide film IL2 a isformed on the main surface of the semiconductor wafer SW by, forexample, a plasma chemical vapor deposition (CVD) process so as to coverthe pad electrodes PD. Subsequently, a silicon nitride film IL2 b isformed on the silicon oxide film IL2 a by, for example, a plasma CVDprocess, so that a passivation film IL2 comprised of the silicon oxidefilm IL2 a and the silicon nitride film IL2 b is formed. The passivationfilm IL2 has a function of preventing entering of water or impuritiesfrom outside, and a function of suppressing transmission of α rays. Thesilicon oxide film IL2 a has a thickness of, for example, 0.2 μm, andthe silicon nitride film IL2 b has a thickness of, for example, 0.6 μm.

Subsequently, as illustrated in FIG. 3, the passivation film IL2 isprocessed by a photolithography process and a dry etching process,thereby pad openings CN1, which each allows a portion of the padelectrode PD other than a periphery thereof to be exposed, are formed inthe passivation film IL2.

Subsequently, as illustrated in FIG. 4, a titanium film and a palladiumfilm are sequentially formed on the main surface of the semiconductorwafer SW by, for example, a sputtering process, so that a seed film(base film) UM comprised of the titanium film and the palladium film isformed. The titanium film is provided to prevent diffusion of palladiumto a semiconductor wafer SW side, and the palladium film is provided topromote growth of the electrodeposited gold electrode formed in a laterstep. The titanium film has a thickness of, for example, about 0.175 μm,and the palladium film has a thickness of, for example, about 0.175 μm.

Subsequently, as illustrated in FIG. 5, a resist pattern RP is formed onthe seed film UM by a photolithography process. The resist pattern RPhas an opening CN2 on each pad electrode PD in a plan view, and the seedfilm UM is exposed at a bottom of the opening CN2. A planar size of theopening CN2 is smaller than a planar size of the pad electrode PD andlarger than planar size of the opening CN1. The resist pattern RP has athickness of, for example, about 10 μm.

Subsequently, the electrodeposited gold electrode AP is formed in theinside of the opening CN2 of the resist pattern RP by an electrolyticgold plating process. The electrodeposited gold electrode AP has athickness of, for example, about 3 μm. The electrodeposited goldelectrode AP has a surface roughness of, for example, 0.025 rad or more.A formation method of the electrodeposited gold electrode AP by theelectrolytic gold plating process is described in detail later.

Subsequently, as illustrated in FIG. 6, the resist pattern RP isremoved. Subsequently, the unnecessary (exposed) seed film UM is removedby a wet etching process with the electrodeposited gold electrode AP asa mask. Through the above steps, the electrodeposited gold electrode AP,which is electrically coupled to the pad electrode PD with the seed filmUM therebetween, is substantially completed.

<Formation Method of Electrodeposited Gold Electrode Using First PlatingApparatus>

A formation method of an electrodeposited gold electrode (theelectrodeposited gold electrode AP illustrated in FIG. 5) using a firstplating apparatus according to the first embodiment is now described.The first plating apparatus has a treatment cup that is structured tostir a plating solution with a stirrer.

1. Internal Structure of Treatment Cup of First Plating Apparatus:

An internal structure of the treatment cup of the first platingapparatus is now described with FIGS. 7A and 7B. FIGS. 7A and 7B areeach a major-part section diagram of the treatment cup of the firstplating apparatus, where FIG. 7A is a major-part section diagramillustrating an aspect of the treatment cup of the first platingapparatus when a semiconductor wafer is set therein or removedtherefrom, and FIG. 7B is a major-part section diagram illustrating anaspect of the treatment cup of the first plating apparatus when asemiconductor wafer is subjected to plating.

The treatment cup of the first plating apparatus has a bottom and asidewall, and is defined to be in an erected state where the bottom liesbelow, while being defined to be in an inverted state where the bottomlies above. Specifically, since the treatment cup is vertically turned180 degrees, top and bottom are defined with reference to the erectedstate of the treatment cup regardless of whether the vertical turnoveroccurs or not. While a plating bath exists in the inside of thetreatment cup, a lower side of the plating bath refers to a bottom sideof the plating bath, and an upper side of the plating bath refers to anopened-face side thereof, the opened face being opposed to the bottom ofthe plating bath and to be covered by a lid.

As illustrated in FIG. 7A, the plating bath PT1 exists in the inside ofthe treatment cup TC1. The plating bath PT1 has a bottom BO1 and a sideface, and is opened on its side opposed to the bottom BO1. The treatmentcup TC1 has a lid TO that is configured to cover the opened face of theplating bath PT1.

The semiconductor wafer SW is set on the upper side of the plating bathPT1 while a device forming surface (pattern surface, or main surface) isallowed to face the inside of the plating bath PT1. A stirrer SB forstirring a plating solution is provided in the center of the platingbath PT1. The stirrer SB is controlled so as to be rotated within theplating bath PT1.

An anode electrode AE1 is provided between the center and the bottom BO1of the plating bath PT1. The anode electrode AE1 is an indium oxideelectrode or a platinum electrode, for example. An undepicted cathodeelectrode for electrical coupling to the semiconductor wafer SW isprovided in the upper side of the side face of the plating bath PT1.

A liquid outlet PO for discharging the plating solution is provided inthe bottom BO1 of the plating bath PT1. A liquid inlet PI1 forintroducing the plating solution is provided in the side face on a sideupper than the center of the plating bath PT1.

The treatment cup TC1 of the first plating apparatus has a verticalturnover mechanism. Specifically, when the semiconductor wafer SW is setin the treatment cup TC1, or when the semiconductor wafer SW isextracted from the treatment cup TC1, as illustrated in FIG. 7A, thedevice forming surface of the semiconductor wafer SW faces down(face-down). On the other hand, when the semiconductor wafer SW issubjected to plating, as illustrated in FIG. 7B, the treatment cup TC1is vertically turned over, and the device forming surface of thesemiconductor wafer SW faces up (face-up).

2. Steps of Plating Process:

Steps of a plating process are now described with FIG. 8. FIG. 8 is aprocess flowchart of a plating process using the first platingapparatus.

<Wafer Holding Step (Step S1 of FIG. 8)>

A plurality of semiconductor wafers are held in a wafer holder,so-called Foup, and the wafer holder is set in a load port provided inthe first plating apparatus.

<Alignment Step (Step S2 of FIG. 8)>

A semiconductor wafer on standby in the Foup is extracted andtransferred to a wafer alignment section by a transfer robot, andalignment of the semiconductor wafer is performed in the wafer alignmentsection.

<Preliminary Washing Step (Step S3 of FIG. 8)>

The semiconductor wafer is transferred from the wafer alignment sectionto a washing section by the transfer robot, and is washed by pure waterin the washing section.

<Electrolytic Plating Step (Step S4 of FIG. 8)>

The semiconductor wafer is transferred from the washing section into thetreatment cup of a plating section by the transfer robot, and issubjected to electrolytic plating in the treatment cup.

<Rinsing and Drying Step (Step S5 of FIG. 8)>

The semiconductor wafer is transferred from the treatment cup of theplating section to a rinsing and drying section by the transfer robot,and is rinsed with pure water and spin-dried in the rinsing and dryingsection.

<Wafer Holding Step (Step S6 of FIG. 8)>

The semiconductor wafer is transferred from the rinsing and dryingsection to the former wafer holder or another wafer holder as necessaryby the transfer robot, and is held therein.

3. Formation Method of Electrodeposited Gold Electrode by ElectrolyticGold Plating Process:

A formation method of the electrodeposited gold electrode by theelectrolytic gold plating process (an electrolytic plating step (step S4of FIG. 8)) is now described with FIGS. 7A and 7B, FIGS. 9A and 9B,FIGS. 10A and 10B, and FIG. 11. FIG. 9A is a schematic illustration of arecipe configuration in plating using the first plating apparatus. FIG.9B is a schematic illustration of a recipe configuration in platingusing the first plating apparatus in a comparative investigation by theinventors. FIG. 10A is a section diagram schematically illustrating theelectrodeposited gold electrode. FIG. 10B is a section diagramschematically illustrating an electrodeposited gold electrode in acomparative investigation by the inventors. FIG. 11 includes a graphshowing surface roughness of an electrodeposited gold electrode witheach of energization ON time or energization OFF time as a parameter.

<Operation 1 of Electrolytic Plating Step>

As illustrated in FIG. 7A, the semiconductor wafer SW washed with purewater is transferred into the plating bath PT1 of the treatment cup TC1,and the semiconductor wafer SW is set on the upper side of the platingbath PT1 while the device forming surface is allowed to face the insideof the plating bath PT1. The semiconductor wafer SW is set while beingin the erected state where the bottom of the treatment cup TC1 liesbelow. Subsequently, the lid TO provided for the treatment cup TC1 isclosed to cover the opened face of the plating bath PT1.

<Operation 2 of Electrolytic Plating Step>

The plating solution is supplied through the liquid inlet PI1 providedon the upper side of the treatment cup TC1 (in the side face on a sideupper than the center of the plating bath PT1), so that the inside ofthe plating bath PT1 is filled with the plating solution. The platingsolution is a non-cyanide plating solution, and is, for example, a goldsulfite plating solution (including, as a main component, an aqueoussolution of sodium gold sulfite, ethylene diamine, inorganic acid salts,and other trace additives). The temperature of the plating solution is,for example, about 40° C., and the supply flow rate of the platingsolution is, for example, about 5 litter/min.

<Operation 3 of Electrolytic Plating Step>

As illustrated in FIG. 7B, the treatment cup TC1 is vertically turned180 degrees so as to be into the inverted state. As a result, the bottomof the treatment cup TC1 lies above, and the lid TO covering the openedface of the plating bath PT1 lies below, and thus the device formingsurface of the semiconductor wafer SW faces up. In this operation,energization for electrolytic plating is not performed, i.e., no currentis allowed to flow between the anode electrode AE1 and the cathodeelectrode.

<Operation 4 of Electrolytic Plating Step>

Subsequently, as illustrated in FIG. 9A, the stirrer is normally rotated(counterclockwise rotated) to stir the plating solution (stirring normalrotation 1). At this time, a predetermined current is continuouslyallowed to flow between the anode electrode and the cathode electrode(energization ON). The rotation speed of the stirrer is, for example,about 90 rpm, and the energization ON time is, for example, about 20 to60 sec. This continuous energization allows isotropic crystal growth ofgold on the seed film, resulting in formation of an electrodepositedgold layer.

Subsequently, the normal rotation (counterclockwise rotation) of thestirrer is stopped to switch the stirring direction of the stirrer fromthe normal rotation (counterclockwise rotation) to reverse rotation(clockwise rotation). At this time, no current is allowed to flowbetween the anode electrode and the cathode electrode (energizationOFF). The energization OFF time is, for example, about 2 to 15 sec.

Subsequently, the stirrer is reversely rotated (clockwise rotated) tostir the plating solution (stirring reverse rotation 1). At this time, apredetermined current is continuously allowed to flow between the anodeelectrode and the cathode electrode (energization ON). The rotationspeed of the stirrer is, for example, about 90 rpm, and the energizationON time is, for example, about 20 to 60 sec. This continuousenergization causes isotropic crystal growth of gold with reference to anew point on the electrodeposited gold layer formed through crystalgrowth during the stirring normal rotation 1, so that a newelectrodeposited gold layer is formed.

Subsequently, the reverse rotation (clockwise rotation) of the stirreris stopped to switch the stirring direction of the stirrer from thereverse rotation (clockwise rotation) to the normal rotation(counterclockwise rotation). At this time, no current is allowed to flowbetween the anode electrode and the cathode electrode (energizationOFF). The energization OFF time is, for example, about 2 to 15 sec.

Subsequently, in the same way as the stirring normal rotation 1 and thestirring reverse rotation 1, stirring normal rotation 2 (energizationON), energization OFF, stirring reverse rotation 2 (energization ON),energization OFF, stirring normal rotation 3 (energization ON),energization OFF, and stirring reverse rotation 3 (energization ON) aresequentially performed. Consequently, there is formed anelectrodeposited gold electrode comprised of six electrodeposited goldlayers formed through crystal growth in the respective stirring steps ofthe stirring normal rotation 1, the stirring reverse rotation 1, thestirring normal rotation 2, the stirring reverse rotation 2, thestirring normal rotation 3, and the stirring reverse rotation 3.

While thickness of the electrodeposited gold layer formed in eachstirring step depends on current density, energization time, temperatureof the plating solution, supply flow rate of the plating solution,rotation speed of the stirrer, and the like, the thickness is, forexample, about 0.5 μm, and thickness of the resultant electrodepositedgold electrode is, for example, about 3 μm.

In an existing electrolytic gold plating process, as illustrated in FIG.9B, time for switching the stirring direction of the stirrer, i.e., theenergization OFF time, during which no current is allowed to flowbetween the anode electrode and the cathode electrode, is, for example,about 1 sec. This is to prevent continuous crystal growth of gold frombeing interrupted. In this case, for example, as illustrated in FIG.10B, crystal growth of gold proceeds isotropically, and anelectrodeposited gold electrode APR comprised of gold crystal having arelatively large grain size is formed. During electrolytic plating,however, aging variation in composition of the plating solution occurswith increase in number of times of treatment or in lapse of time frominitial make-up of electrolytic bath. Hence, a surface state of theelectrodeposited gold electrode APR, which is formed through continuouscrystal growth with the energization OFF time of 1 sec, tends to varydue to the aging variation in composition of the plating solution. Ingeneral, as the number of times of treatment or the lapse of time frominitial make-up of electrolytic bath increases, the surface of theelectrodeposited gold electrode APR gradually changes from a rough stateto a smooth state.

On the other hand, in the electrolytic gold plating process using thefirst plating apparatus according to the first embodiment, time forswitching the stirring direction of the stirrer, i.e., the energizationOFF time, during which no current is allowed to flow between the anodeelectrode and the cathode electrode, is, for example, about 2 to 15 sec.In this case, for example, as illustrated in FIG. 10A, when energizationis restarted in each stirring step, crystal growth of gold isotropicallyproceeds with reference to a new point, so that an electrodeposited goldlayer comprised of gold crystal having a relatively small grain size issequentially formed in each stirring step. For example, in comparisonwith the recipe configuration of FIG. 9A, a first electrodeposited goldlayer P1 is formed in the stirring normal rotation 1, a secondelectrodeposited gold layer P2 is formed in the stirring reverserotation 1, a third electrodeposited gold layer P3 is formed in thestirring normal rotation 2, a fourth electrodeposited gold layer P4 isformed in the stirring reverse rotation 2, a fifth electrodeposited goldlayer P5 is formed in the stirring normal rotation 3, and a sixthelectrodeposited gold layer P6 is formed in the stirring reverserotation 3.

Consequently, the electrodeposited gold electrode AP having a roughsurface with significant irregularities can be formed; hence, a surfacestate of the electrodeposited gold electrode AP is less affected byaging variation in composition of the plating solution, and thus theelectrodeposited gold electrode AP is allowed to maintain its roughsurface state.

If the energization OFF time, during which no current is allowed to flowbetween the anode electrode and the cathode electrode, is longer than 15sec, plating process time is relatively long, leading to reduction inthroughput of the plating process. If the energization OFF time isshorter than 2 sec, crystal growth of gold proceeds withoutinterruption; hence, as illustrated in FIG. 10B, gold crystal having arelatively large grain size is grown. Consequently, it is consideredthat an appropriate range of the energization OFF time, during which nocurrent is allowed to flow between the anode electrode and the cathodeelectrode, is, for example, 2 to 15 sec (it will be appreciated that theenergization OFF time is not limited to such a range depending on otherconditions). A range of the energization OFF time suitable for massproduction is considered to be 3 to 11 sec, and besides a range having acentral value between 5 and 7 sec is considered to be most preferred.

While the energization ON time, during which current is allowed to flowbetween the anode electrode and the cathode electrode, is set to belonger than the energization OFF time, if the energization ON time istoo long, an electrodeposited gold layer comprised of gold crystalhaving a relatively large grain size is sequentially formed in eachstirring step, and the electrodeposited gold electrode AP having a roughsurface cannot be formed. Consequently, it is considered that anappropriate range of the energization ON time, during which current isallowed to flow between the anode electrode and the cathode electrode,is, for example, 20 to 60 sec (it will be appreciated that theenergization ON time is not limited to such a range depending on otherconditions).

FIG. 11 includes a graph showing surface roughness of theelectrodeposited gold electrode with each of the energization ON timeand the energization OFF time as a parameter, and a table collectivelyshowing the energization ON time and the energization OFF time for eachsemiconductor wafer. The graph shows measurement results of surfaceroughness of the electrodeposited gold electrode, the roughness beingmeasured at nine points in a plane of each semiconductor wafer.

As illustrated in FIG. 11, comparing between wafer Nos. #01 and Refsuggests that providing energization OFF time longer than 1 secincreases surface roughness of the electrodeposited gold electrode.Comparing between wafer Nos. #01, #02, and #03 suggests that shorterenergization ON time increases surface roughness of the electrodepositedgold electrode. For example, while the average of surface roughness ofwafer No. Ref 0.027 rad, the average of surface roughness of wafer No.#01 (energization ON time: 59 sec) is 0.032 rad, the average of surfaceroughness of wafer No. #02 (energization ON time: 29 sec) 0.033 rad, andthe average of surface roughness of wafer No. #03 (energization ON time:20 sec) 0.038 rad. In this way, plating is performed while theenergization OFF time of about 2 to 15 sec is provided and theenergization ON time is set short, thereby the electrodeposited goldelectrode AP having a rough surface can be formed.

Although the first embodiment is described with six stirring steps,i.e., the stirring normal rotation 1, the stirring reverse rotation 1,the stirring normal rotation 2, the stirring reverse rotation 2, thestirring normal rotation 3, and the stirring reverse rotation 3, thenumber of stirring steps is not limited thereto. For example, the numberof stirring steps is determined in consideration of thickness of theelectrodeposited gold electrode AP, surface roughness of theelectrodeposited gold electrode AP, parameters of plating (for example,current density, energization time, temperature of the plating solution,supply flow rate of the plating solution, and rotation speed of thestirrer), throughput of the plating process, and the like.

Although it is defined that stirring normal rotation is counterclockwiserotation and stirring reverse rotation is clockwise rotation in thefirst embodiment, the reverse is also acceptable, i.e., it may bedefined that stirring normal rotation is clockwise rotation and stirringreverse rotation is counterclockwise rotation.

<Operation 5 of Electrolytic Plating Step>

As illustrated in FIG. 7A, after supply of the plating solution into theplating bath PT1 is stopped, the treatment cup TC1 is vertically turned180 degrees so as to be into the erected state. As a result, the bottomof the treatment cup TC1 lies below, and the lid TO covering the platingbath PT1 lies above, and thus the device forming surface of thesemiconductor wafer SW faces down.

<Operation 6 of Electrolytic Plating Step>

The plating solution is discharged from the inside of the plating bathPT1 through the liquid outlet PO. Since the treatment cup TC1 is in theerected state, the plating solution flows from the upper side of theplating bath PT1 to the lower side thereof, and is discharged from thebottom of the treatment cup TC1.

<Operation 7 of Electrolytic Plating Step>

The lid TO covering the opened face of the plating bath PT1 is opened toextract the semiconductor wafer SW from the treatment cup TC1.

4. Modification of Formation Method of Electrodeposited Gold Electrodeby Electrolytic Gold Plating Process:

In the above-described 3. formation method of electrodeposited goldelectrode by electrolytic gold plating process (<operation 4 ofelectrolytic plating step>), it is described that plating is performedwhile the energization OFF time of about 2 to 15 sec is provided and theenergization ON time is set short, thereby the electrodeposited goldelectrode having a rough surface can be formed. A modification of themethod of forming the electrodeposited gold electrode having a roughsurface is now described using Table 1. Table 1 summarily shows arelationship between energization ON time, current density, and surfaceroughness of the electrodeposited gold electrode.

TABLE 1 CURRENT DENSITY LOW HIGH ENERGIZATION SHORT HIGH SURFACE MIDDLEON TIME ROUGHNESS SURFACE ROUGHNESS LONG MIDDLE SURFACE LOW SURFACEROUGHNESS ROUGHNESS

When the energization ON time in plating is short, gold crystal having arelatively small grain size is grown. When current density in plating islow, plating rate (crystal growth rate of gold) is slowed, making itpossible to suppress grain growth of gold crystal. Hence, as shown inTable 1, plating is performed with short energization ON time and lowcurrent density, thereby the surface of the electrodeposited goldelectrode can be roughened.

Furthermore, if plating is performed with short energization ON time andlow current density while the energization OFF time of about 2 to 15 secis provided, an electrodeposited gold electrode having a further roughsurface can be formed.

<Formation Method of Electrodeposited Gold Electrode Using SecondPlating Apparatus>

A formation method of an electrodeposited gold electrode (theelectrodeposited gold electrode AP illustrated in FIG. 5) using a secondplating apparatus according to the first embodiment is now described.The second plating apparatus has a treatment cup that is structured tostir a plating solution with a jet.

1. Internal Structure of Treatment Cup of Second Plating Apparatus:

An internal structure of the treatment cup of the second platingapparatus is described with FIG. 12. FIG. 12 is a major-part sectiondiagram of the treatment cup of the second plating apparatus.

As illustrated in FIG. 12, the treatment cup TC2 of the second platingapparatus has a bottom and a sidewall, and a plating bath PT2 exists inthe inside of the treatment cup TC2. The plating bath PT2 has a bottomBO2 and a side face, and is opened on its side opposed to the bottomBO2. The semiconductor wafer SW is set on the upper side of the platingbath PT2 while a device forming surface is allowed to face the inside ofthe plating bath PT2.

An anode electrode AE2 is provided on a bottom BO2 side of the platingbath PT2. The anode electrode AE2 is an indium oxide electrode or aplatinum electrode, for example. A cathode electrode CE for electricalcoupling to the semiconductor wafer SW is provided in the upper side ofthe side face of the plating bath PT2. A liquid inlet PI2 forintroducing a plating solution is provided in the center of the bottomB02 of the plating bath PT2. The plating solution supplied through theliquid inlet PI2 vigorously flows within the plating bath PT2, and isdischarged from the upper side of the plating bath PT2.

The second plating apparatus is not vertically turned over unlike thefirst plating apparatus. Hence, the device forming surface of thesemiconductor wafer SW usually (in each of the cases where thesemiconductor wafer SW is set in the treatment cup, where thesemiconductor wafer SW is extracted from the treatment cup, and wherethe semiconductor wafer SW is subjected to plating) faces down(face-down).

2. Formation Method of Electrodeposited Gold Electrode by ElectrolyticGold Plating Process:

A formation method of the electrodeposited gold electrode by theelectrolytic gold plating process (an electrolytic plating step (step S4of FIG. 8)) is now described with FIGS. 10A and 10B, FIG. 12, and FIGS.13A and 13B. FIG. 13A is a schematic illustration of a recipeconfiguration in plating using the second plating apparatus. FIG. 13B isa schematic illustration of a recipe configuration in plating using thesecond plating apparatus in a comparative investigation by theinventors.

<Operation 1 of Electrolytic Plating Step>

As illustrated in FIG. 12, the semiconductor wafer SW washed with purewater is transferred into the plating bath PT2 of the treatment cup TC2,and the semiconductor wafer SW is set on the upper side of the platingbath PT2 while the device forming surface is allowed to face the insideof the plating bath PT2. In addition, the opened face of the platingbath PT2 is covered by the semiconductor wafer SW. The periphery of thedevice forming surface of the semiconductor wafer SW comes into contactwith the cathode electrode CE.

<Operation 2 of Electrolytic Plating Step>

As illustrated in FIG. 12, the plating solution is supplied through theliquid inlet PI2 provided in the bottom of the treatment cup TC2, andthe plating solution in the plating bath PT2 is stirred with a jet. Theplating solution is a non-cyanide plating solution, and is, for example,a gold sulfite plating solution (including, as a main component, anaqueous solution of sodium gold sulfite, ethylene diamine, inorganicacid salts, and other trace additives). In this operation, energizationfor electrolytic plating is not performed, i.e., no current is allowedto flow between the anode electrode AE2 and the cathode electrode CE.

<Operation 3 of Electrolytic Plating Step>

As illustrated in FIG. 13A, a predetermined current is allowed to flowbetween the anode electrode and the cathode electrode for apredetermined time (energization ON). The energization ON time is, forexample, about 20 to 60 sec. This continuous energization allowsisotropic crystal growth of gold on the seed film, resulting information of a first electrodeposited gold layer.

Subsequently, the energization between the anode electrode and thecathode electrode is suspended (energization OFF) to suspend crystalgrowth of gold. The energization OFF time is, for example, about 2 to 15sec.

Subsequently, a predetermined current is allowed to flow again betweenthe anode electrode and the cathode electrode for a predetermined time(energization ON). The energization ON time is, for example, about 20 to60 sec. During this operation, crystal growth of gold isotropicallyproceeds with reference to a new point on the previously formed, firstelectrodeposited gold layer, and a second electrodeposited gold layer isformed.

Subsequently, the energization between the anode electrode and thecathode electrode is suspended (energization OFF) to suspend crystalgrowth of gold. The energization OFF time is, for example, about 2 to 15sec.

Subsequently, the energization ON and the energization OFF arealternately repeated, thereby an electrodeposited gold electrode APcomprised of a plurality of electrodeposited gold layers in the stack isformed as illustrated in FIG. 10A.

As illustrated in FIG. 13B, when energization OFF time is not providedto prevent continuous crystal growth of gold from being interrupted, forexample, as illustrated in FIG. 10B, an electrodeposited gold electrodeAPR comprised of gold crystal having a relatively large grain size isformed. As described above, during electrolytic plating, aging variationin composition of the plating solution occurs with increase in number oftimes of treatment or in lapse of time from initial make-up ofelectrolytic bath. Hence, a surface state of the electrodeposited goldelectrode APR formed through crystal growth without providing theenergization OFF time tends to vary due to the aging variation incomposition of the plating solution. In general, as the number of timesof treatment or the lapse of time from initial make-up of electrolyticbath increases, the surface of the electrodeposited gold electrode APRgradually changes from a rough state to a smooth state.

On the other hand, in the electrolytic gold plating process using thesecond plating apparatus according to the first embodiment, for example,as illustrated in FIG. 10A, an electrodeposited gold electrode AP isconfigured of stacked electrodeposited gold layers each being comprisedof gold crystal having a relatively small grain size. Consequently, theelectrodeposited gold electrode AP having a rough surface withsignificant irregularities can be formed; hence, the surface state ofthe electrodeposited gold electrode AP is less affected by agingvariation in composition of the plating solution, and thus theelectrodeposited gold electrode AP is allowed to maintain its roughsurface state.

It is considered that an appropriate range of the energization OFF time,during which no current is allowed to flow between the anode electrodeand the cathode electrode, is, for example, 2 to 15 sec (it will beappreciated that the energization OFF time is not limited to such arange depending on other conditions) as with the first platingapparatus. A range of the energization OFF time suitable for massproduction is considered to be 3 to 11 sec, and besides a range having acentral value between 5 and 7 sec is considered to be most preferred.

It is considered that an appropriate range of the energization ON time,during which current is allowed to flow between the anode electrode andthe cathode electrode, is, for example, 20 to 60 sec (it will beappreciated that the energization ON time is not limited to such a rangedepending on other conditions) as with the first plating apparatus.

Although the energization ON time is divided in six in the firstembodiment, this is not limitative. For example, the number of times ofthe energization ON time is determined in consideration of thickness ofthe electrodeposited gold electrode AP, surface roughness of theelectrodeposited gold electrode, parameters of plating (for example,current density, energization time, temperature of the plating solution,supply flow rate of the plating solution, and rotation speed of thestirrer), throughput of the plating process, and the like.

<Operation 4 of Electrolytic Plating Step>

After supply of the plating solution into the plating bath PT2 isstopped, the semiconductor wafer SW is extracted from the treatment cupTC2 (see FIG. 12).

<Effects of First Embodiment>

In this way, according to the first embodiment, even if aging variationin composition of the plating solution occurs with increase in number oftimes of treatment or lapse of time from initial make-up of electrolyticbath during electrolytic plating, variation in surface state of theelectrodeposited gold electrode AP is suppressed, and a surface statewith a surface roughness of, for example, 0.025 rad or more can bemaintained. Consequently, even if gold precipitation (which is notnecessary to be determined to be anomalous in appearance inspection)occurs in a step of forming an electrodeposited gold electrode, theelectrodeposited gold electrode can be determined to be normal inappearance while such gold precipitation is not recognized in appearanceinspection; hence, false reports on appearance inspection of asemiconductor device can be decreased.

Although the invention achieved by the inventors has been described indetail according to an embodiment hereinbefore, the invention should notbe limited thereto, and it will be appreciated that variousmodifications or alterations thereof may be made within the scopewithout departing from the spirit of the invention.

For example, although the above-described embodiment has been describedwith formation of an electrodeposited gold electrode, it will beappreciated that the invention can also be applied to formation of anelectrodeposited copper electrode or an electrodeposited nickelelectrode.

Moreover, although the above-described embodiment has been describedwith an electrodeposited gold electrode having an OPM structure, whichis to be electrically coupled to a pad electrode, it will be appreciatedthat the invention can also be applied to formation of a gold bumpelectrode.

What is claimed is:
 1. A method of manufacturing a semiconductor device,comprising the step of: (a) forming an electrodeposited electrode over amain surface of a semiconductor wafer provided in a plating solutionbath with an anode electrode in a treatment cup, wherein (a) includesthe steps of: (a1) performing energization where current continuouslyflows for at least 20 sec. between the anode electrode and thesemiconductor wafer to cause crystal growth of an electrodeposited goldlayer over the main surface of the semiconductor wafer, and (a2)performing non-energization where the current does not flow for at least2 sec. between the anode electrode and the semiconductor wafer, andwherein the step (a1) and the step (a2) are alternately repeated aplurality of times, and the electrodeposited electrode is formed byrepeating the step (a1) directly followed by the step (a2) to form astack of electrodeposited gold layers which comprise theelectrodeposited electrode, and wherein each of the electrodepositedgold layers is 0.5 μm thick.
 2. The method according to claim 1, whereina non-energization time in the step (a2) is 2 to 15 sec.
 3. The methodaccording to claim 1, wherein a non-energization time in the step (a2)is 3 to 11 sec.
 4. The method according to claim 1, wherein anon-energization time in the step (a2) is 5 to 7 sec.
 5. The methodaccording to claim 1, wherein an energization time in the step (a1) islonger than a non-energization time in the step (a2).
 6. The methodaccording to claim 1, wherein an energization time in the step (a1) is20 to 60 sec.
 7. The method according to claim 1, wherein theelectrodeposited electrode includes one of gold, copper, and nickel as amain component.
 8. The method according to claim 1, further comprisingthe steps of: before the step (a), (b) forming a pad electrode over themain surface of the semiconductor wafer; (c) after the step (b), formingan insulating film over the main surface of the semiconductor wafer soas to cover the pad electrode; (d) after the step (c), forming anopening in the insulating film to expose a top of the pad electrode, and(e) after the step (d), forming a seed film over the main surface of thesemiconductor wafer, wherein the electrodeposited electrode is formedover the seed film.
 9. The method according to claim 8, wherein the padelectrode comprises an aluminum film, and the seed film comprises astacked film including a titanium film and a palladium film formed inorder.
 10. The method according to claim 1, wherein the plating solutionis stirred by a stirrer in the step (a1), and wherein a direction ofstirring by the stirrer is reversed when repeating the step (a1).
 11. Amethod of manufacturing a semiconductor device, comprising: (a) formingan electrodeposited gold electrode over a main surface of asemiconductor wafer provided in a gold sulfite plating solution bathwith a non-gold anode electrode in a treatment cup, wherein (a) includesthe steps of: (a1) performing energization where current continuouslyflows for at least 20 sec. between the anode electrode and thesemiconductor wafer to cause crystal growth of an electrodeposited goldlayer over the main surface of the semiconductor wafer, and (a2)performing non-energization where the current does not flow for at least2 sec. between the anode electrode and the semiconductor wafer, andwherein the step (a1) and the step (a2) are alternately repeated, andthe electrodeposited electrode is formed by repeating the step (a1)directly followed by the step (a2) to form a stack of electrodepositedgold layers which comprise the electrodeposited electrode, wherein eachof the electrodeposited layers is 0.5 μm thick, and the electrodepositedelectrode is 3 μm thick, and wherein a direction of stirring the goldsulfite plating solution bath is alternately reversed when repeating thestep (a1).
 12. The method according to claim 1, wherein theelectrodeposited electrode has a surface roughness of 0.025 rad or more.13. The method according to claim 11, wherein the electrodepositedelectrode has a surface roughness of 0.025 rad or more.